Investigation of the range of numbers of the acyclic model compiler with logical OR and XOR elements in the last digit
Keywords:
acyclic adder with logical elements OR in the last digit, acyclic graph, Kogge-Stone Adder, Han-Carlson Adder
Abstract
The conducted researches have established the prospect of increasing the productivity of calculating the sum signals and transferring acyclic combiners of binary codes with OR logic elements in the last digit. The relationship between the number of computational steps of an oriented acyclic graph and the number of unit transitions to the senior level uniquely determines the minimum number of transitions for the operation of adding binary codes in the scheme of a parallel adder with a parallel transfer method.
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http://journals.uran.ua/tarp/article/view/133694
Kogge P., Stone H. A parallel algorithm for the efficient solution of a general class of recurrence equations // IEEE Tr. Comp., C-22(8): Aug. 1973, pp. 786–793.
Ladner R. E., Fischer M. J. Parallel prefix computation // Journal of the ACM, 27(4): Oct. 1980. pp. 831–838.
Choi, Y. Parallel Prefix Adder Design with Matrix Representation // Proc. 17th IEEE Symposium on Computer Arithmetic, 27th. June 2005, pp 90-98.
Solomko M., Olshansky Р. The Parallel Acyclic Adder // 2017 14th International Conference The Experience of Designing and Application of CAD Systems in Microelectronics (CADSM), Lviv, 2017, рр. 125-129.
Srinivasarao B.N., Prathyusha Ch. Power Efficient Parallel Prefix Adders // International Journal of Research, 2018, February. рр. 472-477. URL:
http://scholar.google.com.ua/scholar_url?
url=https://pen2print.org/index.php/ijr/article/download/12158/11483&hl=uk&sa=X&d=7093867988941575373&scisig=AAGBfm2PGwrG0bBN99RZuzx6QcF2cRUpnA&nossl=1&oi=scholaralrt
Karthik K., Rajeshwar B. A New Design for Variable Latency Speculative EC &D Han-Carlson Adder // International Journal of Research, Volume 04, Issue 13. October 2017. pp. 975-980. URL:
http://scholar.google.com.ua/scholar_url?url=https://pen2print.org/index.php/ijr/article/download/9332/8980&hl=uk&sa=X&d=5289417270700682252&scisig=AAGBfm2SRr4V6L-sliX7AyD4DsUamxYCSA&nossl=1&oi=scholaralrt
Hima Bindu Challa, Srujana Gollapalli, Dr. Varaprasada Rao . M. Design-of-a-novel-BCD-adder-using-parallel-prefix technique // INTERNATIONAL JOURNAL OF RESEARCH IN ELECTRONICS AND COMPUTER ENGINEERING, VOL. 6, ISSUE 2. APR.-JUNE 2018. pp. 2213-2219. URL: https://www.researchgate.net/profile/Srujana_Gollapalli/publication/329425015_Design_of_a_novel_BCD_adder_using_parallel_prefix_technique/links/5c07f505299bf139c741adb5/Design-of-a-novel-BCD-adder-using-parallel-prefix-technique.pdf
Balasubramanian P., Jacob Prathap Raj C., Anandi S. Mathematical Modeling of Timing Attributes of Self-Timed Carry Select Adders // Recent Advances in Circuits, Systems, Telecommunications and Control. 2013. рр. 228-243. URL: http://www.wseas.us/e-library/conferences/2013/Paris/CCTC/CCTC-34.pdf
Nagaraja Revanna, Earl E. Swartzlander Memristor Adder Design // IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS). 5-8 Aug. 2018. URL: https://ieeexplore.ieee.org/abstract/document/8623864
Soares L.B., Azevedo da Rosa M.M. Design Methodology to Explore Hybrid Approximate Adders for Energy-Efficient Image and Video Processing Accelerators // IEEE Transactions on Circuits and Systems I: Regular Papers ( Early Access ). 31 January 2019. рр. 1-14. URL:
https://ieeexplore.ieee.org/abstract/document/8630652
Solomko M., Krulikovskyi B. Study of carry optimization while adding binary numbers in the rademacher number-theoretic basis // Eastern-European Journal of Enterprise Technologies. Mathematics and Cybernetics – applied aspects, Volume 3, № 4(81). 2016. pp: 56-63. URL: http://journals.uran.ua/eejet/article/view/70355
Solomko M. Optimization of the acyclic adders of binary codes // Technology audit and production reserves, Vol 3/2 (41). 2018. pp 55 - 65. URL:
http://journals.uran.ua/tarp/article/view/133694
Abstract views: 1382 PDF Downloads: 99
Published
2020-03-04
How to Cite
ZamriyВ. (2020). Investigation of the range of numbers of the acyclic model compiler with logical OR and XOR elements in the last digit. COMPUTER-INTEGRATED TECHNOLOGIES: EDUCATION, SCIENCE, PRODUCTION, (34), 37-46. Retrieved from https://cit.lntu.edu.ua/index.php/cit/article/view/91
Section
Automation and Control
