Comprehensive Methodology for Optimizing Vhdl Program Code when Designing a Programmable Integrated Circuit

Abstract

An analysis of approaches used in optimizing information systems based on field-programmable gate arrays described by software algorithms developed using VHDL is conducted. The fundamental principles of optimization were determined through the representation of the project logic and functional modeling of the FPGA in accordance with the declared functionality and operating conditions. The transition from high-level to low-level representation in the design of logical blocks of the FPGA, carried out at the compilation stage, allows for the determination of the number of logic elements. Consequently, functional modeling assesses the architecture of the circuit and forms methodological recommendations. The application of a comprehensive optimization methodology based on the conducted analysis enables the increase of task execution speed using the developed FPGA, avoids the risks of excessive logic generation, simplifies arithmetic operations and logical expressions, removes blocks of code that are not executed due to project modifications, applies process parallelization tools, and structures code blocks to reduce the risk of errors during compilation. The tools introduced within the study included the addition of variables and constants to the code, reduction of code volume within loop bodies, removal of unnecessary code blocks in conditional constructions, structuring of arithmetic operations and logical expressions, as well as appropriate partitioning of code blocks. A separate task lies in the optimization of the arithmetic logic unit block of the FPGA, which allows for the reduction of resource consumption, the reduction of the number of logic gates, the mitigation of error risks due to signal delay in opcode delivery, and the establishment of resource sharing among individual components of logical blocks. The developed methodology, thus, serves as the basis for forming a comprehensive set of approaches for generating a logical circuit through VHDL code optimization in accordance with the requirements set during FPGA design.